The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Feature • Outputs Source/Sink 24 mA Pin Arrangement MR 1 Q0 2 D0 3 D.
he Master Reset (MR ) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs MR L H H H H : L : X : : L High Voltage Level Low Voltage Level Immaterial Low-to-High Transition of Clock CP X D X H L X Output Q L H L Q 2 HD74AC174 Logic Diagram MR CP D5 D4 D3 D2 D1 D0 D Q D Q D Q D Q D Q D Q CP CD CP CD CP CD CP CD CP CD CP CD Q5 Q4 Q3 Q2 Q1 Q0 Please note that this diagram is provided only for th.
The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74AC175 |
Hitachi Semiconductor |
Quad D-Type Flip-Flop | |
2 | HD74AC175 |
Renesas |
Quad D-Type Flip-Flop | |
3 | HD74AC107 |
Hitachi Semiconductor |
Dual JK Flip-Flop (with Separate Clear and Clock) | |
4 | HD74AC107 |
Renesas |
Dual JK Flip-Flop | |
5 | HD74AC112 |
Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop | |
6 | HD74AC112 |
Renesas |
Dual JK Negative Edge-Triggered Flip-Flop | |
7 | HD74AC123A |
Hitachi Semiconductor |
Dual Retriggerable Resettable Multivibrator | |
8 | HD74AC123A |
Renesas |
Dual Retriggerable Resettable Multivibrator | |
9 | HD74AC125 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output | |
10 | HD74AC125 |
Renesas |
Quad Buffer/Line Driver | |
11 | HD74AC126 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output | |
12 | HD74AC126 |
Renesas |
Quad Buffer/Line Driver |