The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • Outputs Source/Sink 24 mA • HD74ACT125 has TTL-Compatible Inputs Pin Arran.
• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
• Outputs Source/Sink 24 mA
• HD74ACT125 has TTL-Compatible Inputs
Pin Arrangement
E 1 D 2 O 3 E 4 D 5 O 6 GND 7 (Top view)
14 VCC 13 E 12 D 11 O 10 E 9 D 8 O
HD74AC125/HD74ACT125
Logic Symbol
D
O
E
Pin Names
D E O Data Inputs 3-State Output Enable Inputs (Active Low) Outputs
Truth Table
Inputs E L L H H L X Z : : : : High Voltage Level Low Voltage Level Immaterial High Impedance D L H X Output L H Z
DC Characteristics (unless otherwise specified)
Item Maximum quiescent supply current Maximum quiescent supply curren.
The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock dri.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74AC123A |
Hitachi Semiconductor |
Dual Retriggerable Resettable Multivibrator | |
2 | HD74AC123A |
Renesas |
Dual Retriggerable Resettable Multivibrator | |
3 | HD74AC126 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output | |
4 | HD74AC126 |
Renesas |
Quad Buffer/Line Driver | |
5 | HD74AC107 |
Hitachi Semiconductor |
Dual JK Flip-Flop (with Separate Clear and Clock) | |
6 | HD74AC107 |
Renesas |
Dual JK Flip-Flop | |
7 | HD74AC112 |
Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop | |
8 | HD74AC112 |
Renesas |
Dual JK Negative Edge-Triggered Flip-Flop | |
9 | HD74AC138 |
Hitachi Semiconductor |
1-of-8 Decoder/Demultiplexer | |
10 | HD74AC138 |
Renesas |
1-of-8 Decoder/Demultiplexer | |
11 | HD74AC139 |
Hitachi Semiconductor |
Dual 1-of-4 Decoder/Demultiplexer | |
12 | HD74AC139 |
Renesas |
Dual 1-of-4 Decoder/Demultiplexer |