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The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter inf.
• Outputs Source/Sink 24 mA
• HD74ACT107 has TTL-Compatible Inputs
• Ordering Information: Ex. HD74AC107
Part Name
Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC107FPEL SOP-14 pin (JEITA) FP-14DAV
FP
EL (2,000 pcs/reel)
HD74AC107RPEL SOP-14 pin (JEDEC) FP-14DNV
RP
EL (2,500 pcs/reel)
Notes: 1. Please consult th.
HD74AC107 - Hitachi Semiconductor
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master .
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | HD74AC112 |
Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop |
|
| 2 | HD74AC112 |
Renesas |
Dual JK Negative Edge-Triggered Flip-Flop |
|
| 3 | HD74AC123A |
Hitachi Semiconductor |
Dual Retriggerable Resettable Multivibrator |
|
| 4 | HD74AC123A |
Renesas |
Dual Retriggerable Resettable Multivibrator |
|
| 5 | HD74AC125 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output |
|
| 6 | HD74AC125 |
Renesas |
Quad Buffer/Line Driver |
|
| 7 | HD74AC126 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output |
|
| 8 | HD74AC126 |
Renesas |
Quad Buffer/Line Driver |
|
| 9 | HD74AC138 |
Hitachi Semiconductor |
1-of-8 Decoder/Demultiplexer |
|
| 10 | HD74AC138 |
Renesas |
1-of-8 Decoder/Demultiplexer |
|
| 11 | HD74AC139 |
Hitachi Semiconductor |
Dual 1-of-4 Decoder/Demultiplexer |
|
| 12 | HD74AC139 |
Renesas |
Dual 1-of-4 Decoder/Demultiplexer |
|