HD74AC112 - Hitachi Semiconductor

HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times.

Features

individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features
• Outputs Source/Sink 24 mA
• HD74ACT112 has TTL-Compatible Inputs Pin Arrangement CP1 1 K1 2 J1 3 SD1 4 Q1 5 Q1 6 Q2 7 GND 8 (Top view) 16 VCC 15 CD1 14 CD2 13 CP2 .