Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output pulse p.
retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output pulse period (Q High, Q Low) can be made as long as desired. Alternatively, a delay period can be terminated at any time by a Low signal on CD, which also inhibits triggering. An internal connection from CD to the input gate makes it possible to trigger the circuit by a positive-goin.
Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct C.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HD74AC125 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output | |
2 | HD74AC125 |
Renesas |
Quad Buffer/Line Driver | |
3 | HD74AC126 |
Hitachi Semiconductor |
Quad Buffer/Line Driver with 3-State Output | |
4 | HD74AC126 |
Renesas |
Quad Buffer/Line Driver | |
5 | HD74AC107 |
Hitachi Semiconductor |
Dual JK Flip-Flop (with Separate Clear and Clock) | |
6 | HD74AC107 |
Renesas |
Dual JK Flip-Flop | |
7 | HD74AC112 |
Hitachi Semiconductor |
Dual JK Negative Edge-Triggered Flip-Flop | |
8 | HD74AC112 |
Renesas |
Dual JK Negative Edge-Triggered Flip-Flop | |
9 | HD74AC138 |
Hitachi Semiconductor |
1-of-8 Decoder/Demultiplexer | |
10 | HD74AC138 |
Renesas |
1-of-8 Decoder/Demultiplexer | |
11 | HD74AC139 |
Hitachi Semiconductor |
Dual 1-of-4 Decoder/Demultiplexer | |
12 | HD74AC139 |
Renesas |
Dual 1-of-4 Decoder/Demultiplexer |