FDC6302P - Fairchild Semiconductor

FDC6302P Digital FET/ Dual P-Channel

These Dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors in load.

Features

-25 V, -0.12 A continuous, -0.5 A Peak. R DS(ON) = 13 Ω @ VGS= -2.7 V R DS(ON) = 10 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace multiple PNP digital transistors (IMHxA series) with one DMOS FET. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 4 3 5 2 6 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ,TSTG ESD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current TA = 25oC unless other wise noted FDC6302P -25 -8 Units V V A.