BSP205 - NXP

BSP205 P-channel enhancement mode vertical D-MOS transistor

P-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and intended for use in relay, high-speed and line-transformer drivers. FEATURES • Very low RDS(on) • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain PIN CONFIGURATION Marking code B.

Features

• Very low RDS(on)
• Direct interface to C-MOS, TTL, etc.
• High-speed switching
• No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain PIN CONFIGURATION Marking code BSP205 QUICK REFERENCE DATA Drain-source voltage Drain current (DC) Drain-source ON-resistance −ID = 200 mA; −VGS = 10 V Gate threshold voltage RDS(on) −VGS(th) max. max. −VDS −ID max. max. BSP205 60 V 275 mA 10 Ω 3.5 V handbook, halfpage 4 d g 1 Top view 2 3 MAM121 s Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode ver.