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. . 12 1.1 DPLL Features . . . . . . 12 1.2 DPLL Mode Control . . . . . .
• Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces
• Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently configurable through a serial software interface
• DPLL1 provides all the features necessar.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | ZL30120 |
Zarlink Semiconductor |
SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
|
| 2 | ZL30122 |
Zarlink Semiconductor |
SONET/SDH Low Jitter Line Card Synchronizer |
|
| 3 | ZL30123 |
Zarlink Semiconductor |
Low Jitter Line Card Synchronizer |
|
| 4 | ZL30100 |
Zarlink Semiconductor Inc |
T1/E1 System Synchronizer |
|
| 5 | ZL30101 |
Zarlink Semiconductor Inc |
T1/E1 Stratum 3 System Synchronizer |
|
| 6 | ZL30102 |
Zarlink Semiconductor |
T1/E1 Stratum 4/4E Redundant System Clock Synchronizer |
|
| 7 | ZL30105 |
Zarlink Semiconductor |
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer |
|
| 8 | ZL30106 |
Zarlink |
SONET/SDH/PDH Network Interface DPLL |
|
| 9 | ZL30107 |
Zarlink Semiconductor |
GbE Line Card Synchronizer |
|
| 10 | ZL30108 |
Zarlink Semiconductor |
SONET/SDH Network Interface DPLL |
|
| 11 | ZL30109 |
Zarlink Semiconductor |
DS1/E1 System Synchronizer |
|
| 12 | ZL30110 |
Zarlink Semiconductor |
Telecom Rate Conversion DPLL |
|