The ZL30106 SONET/SDH/PDH network interface Digital Phase-Locked Loop (DPLL) provides timing and synchronization for SONET/SDH and PDH network interface cards. The ZL30106 generates SONET/SDH, PDH, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its refe.
• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
• Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
• Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
• Provides a range of clock outputs: - 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | ZL30100 |
Zarlink Semiconductor Inc |
T1/E1 System Synchronizer | |
2 | ZL30101 |
Zarlink Semiconductor Inc |
T1/E1 Stratum 3 System Synchronizer | |
3 | ZL30102 |
Zarlink Semiconductor |
T1/E1 Stratum 4/4E Redundant System Clock Synchronizer | |
4 | ZL30105 |
Zarlink Semiconductor |
T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer | |
5 | ZL30107 |
Zarlink Semiconductor |
GbE Line Card Synchronizer | |
6 | ZL30108 |
Zarlink Semiconductor |
SONET/SDH Network Interface DPLL | |
7 | ZL30109 |
Zarlink Semiconductor |
DS1/E1 System Synchronizer | |
8 | ZL30110 |
Zarlink Semiconductor |
Telecom Rate Conversion DPLL | |
9 | ZL30111 |
Zarlink Semiconductor |
POTS Line Card PLL | |
10 | ZL30112 |
Zarlink Semiconductor |
SLIC/CODEC DPLL | |
11 | ZL30116 |
Zarlink Semiconductor |
SONET/SDH Low Jitter System Synchronizer | |
12 | ZL30117 |
Zarlink Semiconductor |
SONET/SDH Low Jitter Line Card Synchronizer |