ZL30120 - Zarlink Semiconductor

ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer

. . 11 1.1 DPLL Features . . . . . . 11 1.2 DPLL Mode Control . . . . . .

Features

• Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-1244-CORE, GR-253CORE, ITU-T G.813, and compatible with ITU-T G.8261 (formerly G.pactiming) Internal low jitter APLL provides SONET/SDH clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz Synchronous Ethernet output clocks Programmable output synthesizers (P0, P1) generate general purpose clock frequencies from any multiple of 8 kHz up to 100 MHz Jitter performance of <8 ps RMS on the low.