TDA10045H The TDA10045H is a single-chip channel receiver for 2 and 8 kbytes COFDM modulated signals based on the ETSI specification (ETSI 300-744). The device interfaces directly to an IF signal, which could be either 1st or 2nd IF and integrates a 10-bit Analog-to-Digital Converter (ADC), a Numerically Controlled Oscillator (NCO) and a Phase-Locked Loop .
• 2 and 8 kbytes Coded Orthogonal Frequency Division Multiplexer (COFDM) demodulator (fully DVB-T compliant: ETSI 300-744)
• All modes supported, including hierarchical modes
• Fully automatic transmission parameters detection (including Fast Fourier Transformer (FFT) size and guard interval)
• Digital Signal Processor (DSP) based synchronization (software can be upgraded on the fly)
• No extra-host software required
• On-chip 10-bit Analog-to-Digital Converter (ADC)
• 2nd or 1st IF variable analog input
• Only fundamental crystal oscillator required (4 MHz typical ±100 ppm)
• 6, 7 and 8 MHz c.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TDA10046HT |
Philips |
Single-Chip DVB-T Channel Decoder | |
2 | TDA1001B |
NXP |
Interference and noise suppression circuit for FM receivers | |
3 | TDA1001BT |
NXP |
Interference and noise suppression circuit for FM receivers | |
4 | TDA10021HT |
NXP |
DVB-C channel receiver | |
5 | TDA10023HT |
Philips |
Single chip DVB-C/MCNS channel receiver | |
6 | TDA10025HN |
NXP |
Dual cable demodulator | |
7 | TDA1002A |
ETC |
Recording and Playback Amplifier | |
8 | TDA1003A |
Philips |
Motor Regulator and Bias/Erase Oscillator Circuit | |
9 | TDA1005A |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
10 | TDA1005AT |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
11 | TDA1006A |
ETC |
MOTOR REGULATOR WITH AUTOMATIC TAPE END INDICATOR | |
12 | TDA1008 |
NXP |
Gating / Frequency Divider |