TDA1001B TDA1001BT The TDA1001B is a monolithic integrated circuit for suppressing interference and noise in FM mono and stereo receivers. Features • Active low-pass and high-pass filters • Interference pulse detector with adjustable and controllable response sensitivity • Noise detector designed for FM i.f. amplifiers with ratio detectors or quadrature de.
• Active low-pass and high-pass filters
• Interference pulse detector with adjustable and controllable response sensitivity
• Noise detector designed for FM i.f. amplifiers with ratio detectors or quadrature detectors
• Schmitt trigger for generating an interference suppression pulse
• Active pilot tone generation (19 kHz)
• Internal voltage stabilization QUICK REFERENCE DATA Supply voltage (pin 9) Supply current (pin 9) A.F. input signal handling (pin 1) (peak-to-peak value) Input resistance (pin 1) Voltage gain (V1-16/V6-16) Total harmonic distortion Bandwidth Suppression pulse threshold vol.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TDA1001BT |
NXP |
Interference and noise suppression circuit for FM receivers | |
2 | TDA10021HT |
NXP |
DVB-C channel receiver | |
3 | TDA10023HT |
Philips |
Single chip DVB-C/MCNS channel receiver | |
4 | TDA10025HN |
NXP |
Dual cable demodulator | |
5 | TDA1002A |
ETC |
Recording and Playback Amplifier | |
6 | TDA1003A |
Philips |
Motor Regulator and Bias/Erase Oscillator Circuit | |
7 | TDA10045H |
NXP |
DVB-T channel receiver | |
8 | TDA10046HT |
Philips |
Single-Chip DVB-T Channel Decoder | |
9 | TDA1005A |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
10 | TDA1005AT |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
11 | TDA1006A |
ETC |
MOTOR REGULATOR WITH AUTOMATIC TAPE END INDICATOR | |
12 | TDA1008 |
NXP |
Gating / Frequency Divider |