The TDA10023HT is a single chip DVB-C/MCNS channel receiver for 4, 16, 32, 64, 128 and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is sampled by a 10-bit A/D converter. The TDA10023HT performs the clock and the carrier recovery functions. The digital loop filters for both clock and carrier recovery are programmable in ord.
s s s s s s s s s 4,16, 32, 64, 128 and 256 QAM demodulator (ITU-T J.83 annex A-B and C compatible) High performance for 256 QAM especially for direct IF applications On-chip 10-bit ADC On-chip PLL for crystal frequency multiplication (typically 16 MHz crystal) Digital down conversion Programmable half Nyquist filter (roll off = 0.12, 0.13, 0.15 and 0.18) Two PWM AGC outputs with programmable take-over point (for tuner and down converter control) Clock timing recovery, with programmable second order loop filter Variable symbol rate capability from SACLK/64 to SACLK/4 (with low sampling clock: SA.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TDA10021HT |
NXP |
DVB-C channel receiver | |
2 | TDA10025HN |
NXP |
Dual cable demodulator | |
3 | TDA1002A |
ETC |
Recording and Playback Amplifier | |
4 | TDA1001B |
NXP |
Interference and noise suppression circuit for FM receivers | |
5 | TDA1001BT |
NXP |
Interference and noise suppression circuit for FM receivers | |
6 | TDA1003A |
Philips |
Motor Regulator and Bias/Erase Oscillator Circuit | |
7 | TDA10045H |
NXP |
DVB-T channel receiver | |
8 | TDA10046HT |
Philips |
Single-Chip DVB-T Channel Decoder | |
9 | TDA1005A |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
10 | TDA1005AT |
NXP |
FREQUENCY MULTIPLEX PLL STEREO DECODER | |
11 | TDA1006A |
ETC |
MOTOR REGULATOR WITH AUTOMATIC TAPE END INDICATOR | |
12 | TDA1008 |
NXP |
Gating / Frequency Divider |