TC74HC11AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC11AP, TC74HC11AF Triple 3-Input AND Gate The TC74HC11A is a high speed CMOS 3-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is c.
• High speed: tpd = 7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 1 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS11
Pin Assignment
TC74HC11AP TC74HC11AF
Weight DIP14-P-300-2.54 SOP14-P-300-1.27A
: 0.96 g (typ.) : 0.18 g (typ.)
IEC Logic Symbol
Start of commercial production
1986-11
1
2014-03-01
Truth Table
TC74HC11AP.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TC74HC11AFN |
Toshiba |
Triple 3-Input AND Gate | |
2 | TC74HC11AP |
Toshiba |
Triple 3-Input AND Gate | |
3 | TC74HC112AF |
Toshiba Semiconductor |
Dual J-K Flip Flop | |
4 | TC74HC112AFN |
Toshiba Semiconductor |
Dual J-K Flip-Flop | |
5 | TC74HC112AP |
Toshiba Semiconductor |
Dual J-K Flip-Flop | |
6 | TC74HC107AF |
Toshiba |
Dual J-K Flip-Flop | |
7 | TC74HC107AFN |
Toshiba |
DUAL J-K FLIP-FLOP | |
8 | TC74HC107AP |
Toshiba |
Dual J-K Flip-Flop | |
9 | TC74HC109AF |
Toshiba |
Dual J-K Flip-Flop | |
10 | TC74HC109AFN |
Toshiba |
DUAL J-K FLIP-FLOP | |
11 | TC74HC109AP |
Toshiba |
Dual J-K Flip-Flop | |
12 | TC74HC10AF |
Toshiba |
Triple 3-Input NAND Gate |