TC74HC112AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP, TC74HC112AF Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In.
• High speed: fmax = 67 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS112
Pin Assignment
TC74HC112AP TC74HC112AF
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A
: 1.00 g (typ.) : 0.18 g (typ.)
Start of commercial production
1988-05
1
2014-03-01
IEC Logic Symbol
TC74HC112AP/AF
.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TC74HC112AF |
Toshiba Semiconductor |
Dual J-K Flip Flop | |
2 | TC74HC112AP |
Toshiba Semiconductor |
Dual J-K Flip-Flop | |
3 | TC74HC11AF |
Toshiba |
Triple 3-Input AND Gate | |
4 | TC74HC11AFN |
Toshiba |
Triple 3-Input AND Gate | |
5 | TC74HC11AP |
Toshiba |
Triple 3-Input AND Gate | |
6 | TC74HC107AF |
Toshiba |
Dual J-K Flip-Flop | |
7 | TC74HC107AFN |
Toshiba |
DUAL J-K FLIP-FLOP | |
8 | TC74HC107AP |
Toshiba |
Dual J-K Flip-Flop | |
9 | TC74HC109AF |
Toshiba |
Dual J-K Flip-Flop | |
10 | TC74HC109AFN |
Toshiba |
DUAL J-K FLIP-FLOP | |
11 | TC74HC109AP |
Toshiba |
Dual J-K Flip-Flop | |
12 | TC74HC10AF |
Toshiba |
Triple 3-Input NAND Gate |