The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacita.
ation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70511 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM110N08-05 Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data Unit Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea VGS(th) ID(on) VDS =.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SUM110N08-07 |
Vishay Siliconix |
N-Channel 75-V (D-S) MOSFET | |
2 | SUM110N08-07L |
Vishay Siliconix |
N-Channel 75-V (D-S) 175C MOSFET | |
3 | SUM110N08-07P |
Vishay |
N-Channel MOSFET | |
4 | SUM110N02-03P |
Vishay Siliconix |
N-Channel 20-V (D-S) 175 C MOSFET | |
5 | SUM110N03-03 |
Vishay Siliconix |
N-Channel 30-V (D-S) 175C MOSFET | |
6 | SUM110N03-03P |
Vishay Siliconix |
N-Channel 30-V (D-S) 175C MOSFET | |
7 | SUM110N04-03 |
Vishay Siliconix |
N-Channel 40-V (D-S) 200C MOSFET | |
8 | SUM110N04-04 |
Vishay Siliconix |
N-Channel 40-V (D-S) 175C MOSFET | |
9 | SUM110N04-05H |
Vishay Siliconix |
N-Channel MOSFET | |
10 | SUM110N04-2m1P |
Vishay |
N-Channel 40-V (D-S) MOSFET | |
11 | SUM110N04-2M7H |
Vishay Siliconix |
N-Channel 40-V (D-S) 175C MOSFET | |
12 | SUM110N06-04L |
Vishay Siliconix |
N-Channel 60-V (D-S) 200C MOSFET |