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SUM110N08-05 - Vishay Siliconix

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SUM110N08-05 N-Channel 75-V (D-S) 200C MOSFET

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacita.

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ation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70511 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM110N08-05 Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data Unit Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea VGS(th) ID(on) VDS =.

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