SUM110N04-05H - Vishay Siliconix

SUM110N04-05H N-Channel MOSFET

The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capac.

Features

retation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73146 S-60676Rev. B, 01-May-06 www.vishay.com 1 SPICE Device Model SUM110N04-05H Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 3.6 704 0.0046 0.0076 0.0084 0.89 Measured Data Uni.