STP50N06 - ST Microelectronics

STP50N06 N-Channel Enhancement Mode Power MOS Transistor

w w a D . w S a t e e h U 4 t m o .c STP50N06 STP50N06FI N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR R DS(on) < 0.028 Ω < 0.028 Ω ID 50 A 27 A TYPE VDSS 60 V 60 V STP50N06 STP50N06FI s s s s s s s s TYPICAL RDS(on) = 0.022 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE HIGH CURRENT CAPA.

Features

or Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o w w w Parameter t a .D S a e h INTERNAL SCHEMATIC DIAGRAM U 4 t e 1 2 .c m o 1 3 2 ISOWATT220 Value STP50N06 60 60 ± 20 50 35 200 150 1  -65 to 175 175 27 19 200 45 0.3 2000 STP50N06FI Unit V V V A A A (
•) Pulse width limited by safe operating area July 1993 w w w .D a t a Sh ee U 4 t W/o C V o o W m o .c C C 1/10 STP50N06/FI THERMAL DATA TO-220 R thj-case R thj-amb R t hc-sink Tl Thermal Resistance Junction-case Max 1 62.5 0.5 300 Thermal Resistance Junction-ambient.