STP21N05L - ST Microelectronics

STP21N05L N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR

STP21N05L STP21N05LFI N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR TYPE STP21N05L STP21N05LFI s s s s s s s s V DSS 50 V 50 V R DS( on) < 0.085 Ω < 0.085 Ω ID 21 A 14 A TYPICAL RDS(on) = 0.065 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW GATE CHARGE LOGIC LEVEL COMPATIBLE INPUT 175 oC OPERA.

Features

d) Total Dissipation at Tc = 25 C Derating Factor Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature o Value STP21N05LFI 50 50 ± 15 21 14 84 80 0.53  -65 to 175 175 14 9 84 35 0.23 2000 Unit V V V A A A W W/o C V o o C C (
•) Pulse width limited by safe operating area July 1993 1/10 STP21N05L/FI THERMAL DATA TO-220 R thj-cas e Rthj- amb Rt hc- sin k Tl Thermal Resistance Junction-case Max 1.88 62.5 0.5 300 ISOWATT220 4.29 o o o C/W C/W C/W o C Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For S.