DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will .
individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) Q 5(9) CLEAR (CD) 15(14) J 3(11) 1(13) C.
PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/07102BEA Status Packa.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | SN74LS11 |
Motorola |
TRIPLE 3-INPUT AND GATE | |
2 | SN74LS11 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-AND GATES | |
3 | SN74LS113A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
4 | SN74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
5 | SN74LS10 |
Motorola |
TRIPLE 3-INPUT NAND GATE | |
6 | SN74LS10 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
7 | SN74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE | |
8 | SN74LS107A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | |
9 | SN74LS107A |
Texas Instruments |
DUAL J-K FLIP-FLOPS | |
10 | SN74LS109 |
ON Semiconductor |
LOW POWER SCHOTTKY | |
11 | SN74LS109A |
ON Semiconductor |
Dual JK Positive Edge-Triggered Flip-Flop | |
12 | SN74LS109A |
Motorola |
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP |