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SN74LS112A |
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| Part Number | SN74LS112A |
| Manufacturer | Motorola |
| Description | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the ... |
| Features |
individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
SN54/74LS112A
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q 5(9)
CLEAR (CD) 15(14) J 3(11)
1(13) C... |
| Document |
 SN74LS112A Data Sheet
PDF 147.34KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | SN74LS112A |
Texas Instruments |
Dual J-K Negative-Edge-Triggered Flip-Flops |
|
| 2 | SN74LS11 |
Motorola |
TRIPLE 3-INPUT AND GATE |
|
| 3 | SN74LS11 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-AND GATES |
|
| 4 | SN74LS113A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 5 | SN74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|