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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform.
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| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | SN74LS11 |
Motorola |
TRIPLE 3-INPUT AND GATE |
|
| 2 | SN74LS11 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-AND GATES |
|
| 3 | SN74LS112A |
Texas Instruments |
Dual J-K Negative-Edge-Triggered Flip-Flops |
|
| 4 | SN74LS112A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 5 | SN74LS114A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 6 | SN74LS10 |
Motorola |
TRIPLE 3-INPUT NAND GATE |
|
| 7 | SN74LS10 |
Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATES |
|
| 8 | SN74LS10 |
ON Semiconductor |
TRIPLE 3-INPUT NAND GATE |
|
| 9 | SN74LS107A |
Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
|
| 10 | SN74LS107A |
Texas Instruments |
DUAL J-K FLIP-FLOPS |
|
| 11 | SN74LS109 |
ON Semiconductor |
LOW POWER SCHOTTKY |
|
| 12 | SN74LS109A |
ON Semiconductor |
Dual JK Positive Edge-Triggered Flip-Flop |
|