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The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capaci.
al interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC ee DataSh DataSheet4U.com This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. DataSheet4U.com Document Number: 73150 S-50836Rev. B, 16-May-05 www.vishay.com 1 www.DataSheet4U.com SPICE Device Model Si3495DV Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current ba Symbol Test Condition.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | SI3493BDV |
Vishay Siliconix |
P-Channel 20-V (D-S) MOSFET |
|
| 2 | SI3493DDV |
Vishay |
MOSFET |
|
| 3 | SI3493DV |
Vishay Siliconix |
P-Channel 20-V (D-S) MOSFET |
|
| 4 | SI3499DV |
Vishay Siliconix |
P-Channel 1.5-V (G-S) MOSFET |
|
| 5 | SI3400 |
Silicon Laboratories |
FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE AND SWITCHING REGULATOR |
|
| 6 | SI3400A |
MCC |
N-Channel MOSFET |
|
| 7 | SI3401 |
Silicon Laboratories |
FULLY-INTEGRATED 802.3-COMPLIANT PD INTERFACE AND SWITCHING REGULATOR |
|
| 8 | SI3401 |
MCC |
P-Channel MOSFET |
|
| 9 | SI3401 |
ZHONGGUI |
P-Channel MOSFET |
|
| 10 | SI3401A |
MCC |
P-Channel MOSFET |
|
| 11 | SI3402-B |
Silicon Laboratories |
FULLY-INTEGRATED 802.3-COMPLIANT POE PD INTERFACE AND LOW-EMI SWITCHING REGULATOR |
|
| 12 | Si3404 |
Skyworks |
1-Compliant POE PD Interface and High-Efficiency Switching Regulator |
|