The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock output will be nearly zero. This zero-delay feature allows the.
High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation. Maximum clock frequency of 150 MHz. Low jitter: Cycle-to-Cycle jitter ±100ps max Operates at 3.3V VCC Available Packaging: 48-pin TSSOP (Thin Shrink Small Outline) (A) Description The PI6C2516 family is a low-skew, lo.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | PI6C2510-133 |
Pericom Semiconductor Corporation |
Low-Noise/ Phase-Locked Loop Clock Driver with 10 Clock Outputs | |
2 | PI6C2501 |
Pericom Semiconductor |
Phase-Locked Loop Clock Driver | |
3 | PI6C2502 |
Pericom Semiconductor Corporation |
Phase-Locked Loop Clock Driver | |
4 | PI6C2502A |
Pericom Semiconductor Corporation |
Phase-Locked Loop Clock Driver | |
5 | PI6C2504 |
Pericom Semiconductor |
Phase-Locked Loop Clock Driver | |
6 | PI6C2401 |
Pericom Semiconductor |
Phase-Locked Loop Clock Driver | |
7 | PI6C2404A-1 |
Pericom Semiconductor |
Zero-Delay Clock Buffer | |
8 | PI6C2405A |
Pericom Semiconductor Corporation |
Zero-Delay Clock Buffer | |
9 | PI6C2408 |
Pericom Semiconductor Corporation |
3.3V 4+4 Ouptut Zero-delay Clock Driver | |
10 | PI6C2409 |
Pericom Semiconductor Corporation |
Zero-Delay Clock Buffer | |
11 | PI6C2952 |
Pericom Semiconductor |
Low Voltage PLL Clock Driver | |
12 | PI6C2972 |
Pericom Semiconductor Corporation |
Low Voltage PLL Clock Driver |