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The PI6C2504 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Logic Block Diagram G 4 PLL FB_IN AVCC FB_O.
• High-Performance Phase-Locked-Loop Clock Distribution for Networking
• Registered DIMM Synchronous DRAM modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter ±100ps max.
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction
• Operates at 3.3V VCC
• Wide range of Clock Frequencies up to 80 MHz
• Package: Plastic 16-pin QSOP Package (Q)
Product Description
The PI6C2504 features a low-skew, low-jitter, phase-locked loop (PLL) cl.
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|---|---|---|---|---|
| 1 | PI6C2501 |
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| 2 | PI6C2502 |
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| 3 | PI6C2502A |
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