P9NB60FP - ST Microelectronics

P9NB60FP STP9NB60FP

Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charg.

Features

n-source Voltage (VGS = 0) Drain- gate Voltage (RGS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at Tc = 25 o C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) T otal Dissipation at Tc = 25 o C Derating F actor dv/dt( 1 ) Peak Diode Recovery voltage slope V ISO Ts tg Tj Insulation Withstand Voltage (DC) Storage Temperature Max. O perating Junction Temperature o TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM Value STP9NB60 STP9NB60F P 600 600 ± 30 9.0 5.7 36 125 1.0 4.5  -65 to 150 150 ( 1) ISD ≤ 9A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Un it V V V 9.0(
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