P16NS25 - STMicroelectronics

P16NS25 STP16NS25

Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for lighting applications. TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s.

Features

oltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature
  –65 to 150 (1) ISD≤ 16A, di/dt≤300 A/ µs, VDD≤ V(BR)DSS , Tj≤TjMAX (
*) Limited only by maximum temperature allowed Value STP16NS25FP 250 250 ± 20 16 11 64 140 1 5 2500 16(
*) 11(
*) 64(
*) 40 0.33 Unit V V V A A A W W/°C V/ns V °C (
•)Pulse width limited by safe operating area May 200.