NT5DS32M4AW - Nanya Technology

NT5DS32M4AW (NT5DSxxMxAx) 128Mb DDR333/300 SDRAM

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write The 128Mb DDR SDRAM uses a double-data-rate archite.

Features

CAS Latency and Frequency Maximum Operating Frequency (MHz)
* DDR333 DDR300 (-6) (-66) 2 133 133 2.5 166 150
* Values are nominal (exact tCK should be used). CAS Latency
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with.