NT5DS32M8AT - Nanya

NT5DS32M8AT 256Mb DDR333/300 SDRAM

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the bur.

Features

CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz)
* DDR333 (-6) DDR300 (-66) 133 133 166 150
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each posit.