The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# f.
• JEDEC- and industry-standard x16 timing, functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN
• Optional self refresh (S) for low-power data retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets
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No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | MT4C1M16E5 |
Micron Technology |
EDO DRAM | |
2 | MT4C1004J883C |
Austin Semiconductor |
4 MEG x 1 DRAM FAST PAGE MODE | |
3 | MT4C1024 |
Micron Technology |
1M x 1 DRAM | |
4 | MT4C1024-883C |
Micron Technology |
1M x 1 DRAM | |
5 | MT4C1024E |
Micron Technology |
(MT4C1024E / MT4C4256E) 1 MEG PAGE MODE DRAM | |
6 | MT4C1024L |
Micron Technology |
1M x 1 DRAM | |
7 | MT4C1025 |
Micron Technology |
1M x 1 DRAM | |
8 | MT4C1026 |
Micron Technology |
1M x 1 DRAM | |
9 | MT4C1027 |
Micron Technology |
1M x 1 DRAM | |
10 | MT4C16256 |
Micron Technology |
256K x 16 DRAM (MT4C16256/7/8/9) | |
11 | MT4C16270 |
Micron Technology |
DRAM 256K X 16 DRAM 5V / EDO PAGE MODE | |
12 | MT4C40004 |
Micron Technology |
4M x 4 DRAM |