MT4C1004J883C - Austin Semiconductor

MT4C1004J883C 4 MEG x 1 DRAM FAST PAGE MODE

The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits and /C/A/S the latter 11 bits. A READ or WRITE cycle is selected wit.

Features

• Industry standard x1 pinout, timing, functions and packages
• High-performance, CMOS silicon-gate process
• Single +5V ± 10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs and clocks are fully TTL and CMOS compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR), and HIDDEN
• FAST PAGE MODE access cycle www.DataSheet4U.com
• CBR with ?W/E a HIGH (JEDEC test mode capable via WCBR) 2 4 6 8 10 12 14 16 18 20 CAS Vss WE A10
* NC A1 A3 A4 A6 A8 OPTIONS
• Timing 70ns access 80ns access 100ns access 12.