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The MT4C16270 is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x16 configuration. The MT4C16270 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins. The MT4C16270 CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and by the last to transition back HIGH. CASL# and CASH.
• Industry-standard x16 pinouts, timing, functions and packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply
*
• Low power, 3mW standby; 300mW active, typical
• All device pins are TTL-compatible
• 512-cycle refresh in 8ms (9 row- and 9 column addresses)
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN
• Extended Data-Out (EDO) PAGE MODE access cycle
• BYTE WRITE and BYTE READ access cycles
256K x 16 DRAM
5V, EDO PAGE MODE
PIN ASSIGNMENT (Top View) 40-Pin SOJ (DA-6)
OPTIONS
• Timing 40ns access 50ns access 60ns access
• Packages Plastic SOJ (400 mil.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MT4C16256 |
Micron Technology |
256K x 16 DRAM (MT4C16256/7/8/9) |
|
| 2 | MT4C1004J883C |
Austin Semiconductor |
4 MEG x 1 DRAM FAST PAGE MODE |
|
| 3 | MT4C1024 |
Micron Technology |
1M x 1 DRAM |
|
| 4 | MT4C1024-883C |
Micron Technology |
1M x 1 DRAM |
|
| 5 | MT4C1024E |
Micron Technology |
(MT4C1024E / MT4C4256E) 1 MEG PAGE MODE DRAM |
|
| 6 | MT4C1024L |
Micron Technology |
1M x 1 DRAM |
|
| 7 | MT4C1025 |
Micron Technology |
1M x 1 DRAM |
|
| 8 | MT4C1026 |
Micron Technology |
1M x 1 DRAM |
|
| 9 | MT4C1027 |
Micron Technology |
1M x 1 DRAM |
|
| 10 | MT4C1M16C3 |
Micron |
1 MEG x 16 FPM DRAM |
|
| 11 | MT4C1M16E5 |
Micron Technology |
EDO DRAM |
|
| 12 | MT4C40004 |
Micron Technology |
4M x 4 DRAM |
|