MSC8256 - Freescale Semiconductor

MSC8256 Six-Core Digital Signal Processor

Freescale Semiconductor Data Sheet Six-Core Digital Signal Processor Document Number: MSC8256 Rev. 6, 7/2013 MSC8256 FC-PBGA–783 29 mm × 29 mm • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory manageme.

Features

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• Five PLLs (three global and two Serial RapidIO PLLs).
• Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3.
• DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM.
• Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/.