Differential clock frequency input Differential feedback input Bank A outputs Bank B outputs Synchronization output Differential feedback output pull-down pull-down pull-down pull-down pull-up pull-up Selection of operating frequency range Selection of bank A output frequency Selection of bank B output frequency Selection of PLL operation or TEST mode (PLL b.
synchronization purposes and one HSTL compatible PLL feedback output. The device operates from a dual voltage supply: 3.3 V for the core logic and 1.8 V for the HSTL outputs. The fully integrated PLL supports an input frequency range of 75 to 287.5 MHz. The output frequencies are configurable.
MPC9990
LOW VOLTAGE DIFFERENTIAL PECL
–HSTL PLL CLOCK DRIVER
•
•
•
•
•
•
•
•
•
•
•
•
LVPECL compatible clock input, LVCMOS compatible control inputs
The MPC9990 provides output clock frequencies required for high
–performance computer system optimization. The device drives up to 10 differential clock.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | MPC9992 |
Motorola |
3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR | |
2 | MPC990 |
Motorola |
(MPC990 / MPC991) LOW VOLTAGE PLL CLOCK DRIVER | |
3 | MPC992 |
Motorola |
LOW VOLTAGE PLL CLOCK DRIVER | |
4 | MPC993 |
Motorola |
Dynamic Switch PLL Clock Driver | |
5 | MPC99J93 |
Motorola |
Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver | |
6 | MPC9100 |
Motorola |
DUAL PLL CLOCK GENERATOR | |
7 | MPC9108 |
Motorola |
MULTIPLE OUTPUT CLOCK SYNTHESIZER | |
8 | MPC9109 |
Motorola |
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP | |
9 | MPC9109 |
Integrated Device Technology |
Low Voltage 1:18 Clock Distribution Chip | |
10 | MPC911 |
Motorola |
LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/HSTL TO HSTL CLOCK DRIVER | |
11 | MPC9120 |
Motorola |
1:10 LVCMOS FANOUT BUFFER | |
12 | MPC9140 |
Motorola |
1:18 LVCMOS FANOUT BUFFER |