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Pin Name BUF_IN SDRAM0:9 SDATA SCLK OE VDD VSS I/O I O I/O I I – – 3.3V CMOS clock input 3.3V CMOS SDRAM clock outputs Serial data for configuration control Serial clock input for configuration control. The state of the SDATA input is clocked into the device on the rising edge of this clock A Low forces all outputs into High–Z state 3.3V power supply connec.
10 low skew outputs optimized to drive the clock inputs of standard unbuffered SO
–DIMM SDRAM modules. Standard unbuffered SO
–DIMM SDRAM modules require two clocks per module allowing for the device to drive up to four modules. The output buffers have been optimized to drive the load presented by the SDRAM module. The MPC9120 provides output shut off capabilities via an I2C serial port for applications which plan to use fewer than four modules and desire to minimize the power dissipation of the chip. Every output clock can be www.DataSheet4U.com individually enabled/disabled through fields in t.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MPC9100 |
Motorola |
DUAL PLL CLOCK GENERATOR |
|
| 2 | MPC9108 |
Motorola |
MULTIPLE OUTPUT CLOCK SYNTHESIZER |
|
| 3 | MPC9109 |
Motorola |
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
|
| 4 | MPC9109 |
Integrated Device Technology |
Low Voltage 1:18 Clock Distribution Chip |
|
| 5 | MPC911 |
Motorola |
LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/HSTL TO HSTL CLOCK DRIVER |
|
| 6 | MPC9140 |
Motorola |
1:18 LVCMOS FANOUT BUFFER |
|
| 7 | MPC9229 |
Motorola |
400 MHz Low Voltage PECL Clock Synthesizer |
|
| 8 | MPC9230 |
Motorola |
800 MHz Low Voltage PECL Clock Synthesizer |
|
| 9 | MPC9230 |
IDT |
800MHz Low Voltage PECL Clock Synthesizer |
|
| 10 | MPC9239 |
Freescale Semiconductor |
900 MHz Low Voltage LVPECL Clock Synthesizer |
|
| 11 | MPC92429 |
Motorola |
400 MHz Low Voltage PECL Clock Synthesizer |
|
| 12 | MPC92432 |
Motorola |
1360 MHz Dual Output LVPECL Clock Synthesizer |
|