Recherchez avec le numéro de pièce ainsi que le fabricant ou la description
Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compliment PECL reference clock input (Int Pullup) Internal divide.
to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32
–lead TQFP package to optimize both performance and board density.
MPC992 LOGIC DIAGRAM
PLL_EN VCO_SEL XTAL_SEL XTAL1 XTAL2 PECL_CLK PECL_CLK FSEL0 FSEL1 POR XTAL OSC x2 1 0 Integrated PLL 0 1 0 1
Qan Qan Frequenc.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MPC990 |
Motorola |
(MPC990 / MPC991) LOW VOLTAGE PLL CLOCK DRIVER |
|
| 2 | MPC993 |
Motorola |
Dynamic Switch PLL Clock Driver |
|
| 3 | MPC9990 |
Motorola |
Low Voltage PLL Clock Driver |
|
| 4 | MPC9992 |
Motorola |
3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
|
| 5 | MPC99J93 |
Motorola |
Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver |
|
| 6 | MPC9100 |
Motorola |
DUAL PLL CLOCK GENERATOR |
|
| 7 | MPC9108 |
Motorola |
MULTIPLE OUTPUT CLOCK SYNTHESIZER |
|
| 8 | MPC9109 |
Motorola |
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
|
| 9 | MPC9109 |
Integrated Device Technology |
Low Voltage 1:18 Clock Distribution Chip |
|
| 10 | MPC911 |
Motorola |
LOW-VOLTAGE 1:9 DIFFERENTIAL ECL/HSTL TO HSTL CLOCK DRIVER |
|
| 11 | MPC9120 |
Motorola |
1:10 LVCMOS FANOUT BUFFER |
|
| 12 | MPC9140 |
Motorola |
1:18 LVCMOS FANOUT BUFFER |
|