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MPC93R51 - Motorola

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MPC93R51 LOW VOLTAGE PLL CLOCK DRIVER

The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be.

Features

W Application Information The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between the outputs and the reference signal. © Motorola, Inc. 2002 For More Information On This Product, 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC93R51 PCLK PCLK TCLK REF_SEL EXT_FB (pullup) 0 Ref (pulldown) 1 0 PLL 1 ÷2 ÷4 ÷8 0 D 1 Q QA (pulldown) (pulldown) FB 200 - 480 MHz 0 D 1 (pullup) Q.

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