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The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both .
• Fully integrated PLL supports spread spectrum clocking
• Supports applications requiring clock redundancy
• Max. output skew of 120 ps (80 ps within one bank)
• Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)
• 2 selectable LVCMOS clock inputs
• External PLL feedback path and selectable feedback configuration
• Tristable outputs
• 32 ld LQFP package
• Ambient operating temperature range of
–40 to +85°C
Functional Description The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a conne.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | MPC931 |
Motorola |
(MPC930 / MPC931) LOW VOLTAGE PLL CLOCK DRIVER |
|
| 2 | MPC930 |
Motorola |
(MPC930 / MPC931) LOW VOLTAGE PLL CLOCK DRIVER |
|
| 3 | MPC932 |
Motorola |
LOW VOLTAGE PLL CLOCK DRIVER |
|
| 4 | MPC9330 |
Motorola |
3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
|
| 5 | MPC9331 |
Motorola |
3.3 V 1:6 LVCMOS PLL Clock Generator |
|
| 6 | MPC9350 |
Motorola |
LOW VOLTAGE PLL CLOCK DRIVER |
|
| 7 | MPC9352 |
Motorola |
3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
|
| 8 | MPC9352 |
IDT |
3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator |
|
| 9 | MPC93R51 |
Motorola |
LOW VOLTAGE PLL CLOCK DRIVER |
|
| 10 | MPC93R52 |
Motorola |
LOW VOLTAGE 3.3V LVCMOS 1:11 CLOCK GENERATOR |
|
| 11 | MPC9100 |
Motorola |
DUAL PLL CLOCK GENERATOR |
|
| 12 | MPC9108 |
Motorola |
MULTIPLE OUTPUT CLOCK SYNTHESIZER |
|