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LH532100B-1 - Sharp Electrionic Components

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LH532100B-1 CMOS 2M (256K x 8) MROM

The LH532100B-1 is a CMOS 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate process technology. D7 CE A10 OE/OE A11 A9 A8 A13 A14 21 22 23 24 25 26 27 28 29 32-PIN DIP 32-PIN SOP OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND CMOS 2M (256K × 8) MROM PIN CONNECTIONS TOP VIEW 1 2 3 4 5 6 7 8 9 10 11.

Features


• 262,144 words × 8 bit organization
• Access time: 120 ns (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.)
• Mask-programmable control pin: Pin 1 = OE1/OE1/DC Pin 24 = OE/OE
• Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) 32-pin, 8 × 20 mm2 TSOP (Type I) 32-pin, 400-mil TSOP (Type II) DESCRIPTION The LH532100B-1 is a CMOS 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate process technology. D7 CE A10 OE.

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