and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/May. 02 1 www.DataSheet4U.com HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T Revision History 1. Revision 0.2 (Nov.01) 1) Device operation and timing diagram removed 2) tHZ / tLZ SPEC def.
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• VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe
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• All addresses and control inputs except data, data strobes and data masks latched on the r.
and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits desc.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HY5DU281622LT-H |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
2 | HY5DU281622LT-K |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
3 | HY5DU281622LT-L |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
4 | HY5DU281622 |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
5 | HY5DU281622AT |
Hynix Semiconductor |
(HY5DU28xxxAT) 3rd 128M DDR SDRAM | |
6 | HY5DU281622AT-6 |
Hynix Semiconductor |
128M(8Mx16) DDR SDRAM | |
7 | HY5DU281622DT |
Hynix Semiconductor |
(HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM | |
8 | HY5DU281622ET |
Hynix Semiconductor |
128M(8Mx16) GDDR SDRAM | |
9 | HY5DU281622FTP |
Hynix |
128Mb DDR SDRAM | |
10 | HY5DU281622T |
Hynix Semiconductor |
2nd 128M DDR SDRAM | |
11 | HY5DU281622T-H |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
12 | HY5DU281622T-K |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM |