The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is organized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While al.
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• 2.5V V DD and VDDQ power suppliy All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ)
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• Delay Locked Loop(DLL) inst.
No. | Partie # | Fabricant | Description | Fiche Technique |
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1 | HY5DU281622LT-K |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
2 | HY5DU281622LT-L |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
3 | HY5DU281622LT |
Hynix Semiconductor |
(HY5DU28xxxAT) 3rd 128M DDR SDRAM | |
4 | HY5DU281622LT |
Hynix Semiconductor |
(HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM | |
5 | HY5DU281622 |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM | |
6 | HY5DU281622AT |
Hynix Semiconductor |
(HY5DU28xxxAT) 3rd 128M DDR SDRAM | |
7 | HY5DU281622AT-6 |
Hynix Semiconductor |
128M(8Mx16) DDR SDRAM | |
8 | HY5DU281622DT |
Hynix Semiconductor |
(HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM | |
9 | HY5DU281622ET |
Hynix Semiconductor |
128M(8Mx16) GDDR SDRAM | |
10 | HY5DU281622FTP |
Hynix |
128Mb DDR SDRAM | |
11 | HY5DU281622T |
Hynix Semiconductor |
2nd 128M DDR SDRAM | |
12 | HY5DU281622T-H |
Hyundai |
4 Banks x 2M x 16Bit Double Data Rate SDRAM |