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HY5DU281622DT - Hynix Semiconductor

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HY5DU281622DT (HY5DU28xx22D(L)T) 128Mb-S DDR SDRAM

and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Apr. 2003 1 DataSheet4U.com www.DataSheet4U.com HY5DU28422D(L)T HY5DU28822D(L)T HY5DU281622D(L)T Revision History 1. Rev 0.0 (Apr. 2003) 1) Datasheet Release in Preliminary version et4U.c.

Features








• VDD, VDDQ = 2.6V +/- 0.1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS)



• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.5/ 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS et4U.com

• x16 device has two byte.

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