HEF4076B - NXP

HEF4076B Quadruple D-type register with 3-state outputs

The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), two active LOW data enable inputs (ED0 and ED1), a common clock input (CP), four 3-state outputs (O0 to O3), two active LOW output enable inputs (EO0 and EO1), and an overriding asynchronous master reset input (MR). HEF4076B MSI Information on D0 to D3 is stored i.

Features

, independent of the information on D0 to D3. When both EO0 and EO1 are LOW, the contents of the four flip-flops are available at O0 to O3. A HIGH on either EO0 or EO1 forces O0 to O3 into the high impedance OFF-state. A HIGH on MR resets all four flip-flops, independent of all other input conditions. Fig.2 Pinning diagram. HEF4076BP(N): 16-lead DIL; plastic (SOT38-1) HEF4076BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4076BT(D): 16-lead SO; plastic (SOT109-1) Fig.1 Functional diagram. ( ): Package Designator North America PINNING D0 to D3 ED0, ED1 EO0, EO1 CP MR O0 to O3 data inputs dat.