HEF4072B - NXP

HEF4072B Dual 4-input OR gate

The HEF4072B provides the positive dual 4-input OR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4072B gates Fig.2 Pinning diagram. HEF4072BP(N): 14-lead DIL; plastic (SOT27-1) HEF4072BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4072BT(D): 14-lead SO; plastic Fig.1 Functional diagr.

Features

C CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 80 35 25 75 35 25 60 30 20 60 30 20 155 70 55 145 70 55 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4072B gates TYPICAL EXTRAPOLATION FORMULA 53 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 n.