HEF4042B - NXP

HEF4042B Quadruple D-latch

The HEF4042B is a 4-bit latch with four data inputs (D0 to D3), four buffered latch outputs (O0 to O3), four buffered complementary latch outputs (O0 to O3) and two common enable inputs (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 as long as both E0 an.

Features

polarity for E0 and E1. With one enable input HIGH, the other enable input is active HIGH; with one enable input LOW, the other enable input is active LOW. HEF4042B MSI Fig.2 Pinning diagram. HEF4042BP(N): HEF4042BD(F): HEF4042BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D0 to D3 E0 and E1 O0 to O3 O0 to O3 data inputs enable inputs parallel latch outputs complementary parallel latch outputs APPLICATION INFORMATION Some examples of applications for the HEF4042B are:
• Buffer storag.