The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle.
Frequency dividers
• Time delay circuits Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4024BP(N): HEF4024BD(F): HEF4024BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America
January 1995
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No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | HEF40240B |
NXP |
Octal inverting buffers with 3-state outputs | |
2 | HEF40244B |
NXP |
Octal buffers with 3-state outputs | |
3 | HEF40244B |
nexperia |
Octal buffers | |
4 | HEF40245B |
NXP |
Octal bus transceiver with 3-state outputs | |
5 | HEF4020B |
NXP |
14-stage binary counter | |
6 | HEF4020B |
nexperia |
14-stage binary counter | |
7 | HEF4020B-Q100 |
nexperia |
14-stage binary counter | |
8 | HEF4021B |
NXP |
8-bit static shift register | |
9 | HEF4021B |
nexperia |
8-bit static shift register | |
10 | HEF4021B-Q100 |
nexperia |
8-bit static shift register | |
11 | HEF4022B |
NXP |
4-stage divide-by-8 Johnson counter | |
12 | HEF4023B |
NXP |
Triple 3-input NAND gate |