The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 b.
1
•23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered.
• Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
• "Input Clock Detection" Feature Will Pull All LVDS Pairs to Logic Low when Input Clock is Missing and When /PD Pin is Logic High.
• 18 to 68 MHz Shift Clock Support
• Best
–in
–Class Set & Hold Times on TxINPUTs
• Tx Power Consumption < 130 mW (typ)
@65MHz Grayscale
• 40% Less Power Dissipation Than BiCMOS.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | DS90CF383 |
National Semiconductor |
+3.3V LVDS Transmitter | |
2 | DS90CF384 |
National Semiconductor |
+3.3V Programmable LVDS Transmitter | |
3 | DS90CF384A |
National Semiconductor |
+3.3V LVDS Receiver | |
4 | DS90CF384A |
Texas Instruments |
+3.3V LVDS Receiver | |
5 | DS90CF384AQ |
Texas Instruments |
+3.3V LVDS Receiver | |
6 | DS90CF386 |
National Semiconductor |
+3.3V LVDS Receiver | |
7 | DS90CF386 |
Texas Instruments |
3.3-V LVDS Receiver | |
8 | DS90CF388 |
National Semiconductor |
Dual Pixel LVDS Display Interface | |
9 | DS90CF388 |
Texas Instruments |
Dual Pixel LVDS Display Interface | |
10 | DS90CF388A |
National Semiconductor |
Dual Pixel LVDS Display Interface/FPD-Link | |
11 | DS90CF363 |
National Semiconductor |
+3.3V LVDS Transmitter | |
12 | DS90CF363A |
National Semiconductor |
+3.3V Programmable LVDS Transmitter |