The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bi.
n n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 227 Megabytes/sec bandwidth Up to 1.8 Gbps throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Transmitter Compatible with TIA/EIA-644 LVDS standard ESD rating > 7 kV Operating Temperature: −40˚C to .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | DS90CF383B |
Texas Instruments |
+3.3V Programmable LVDS Transmitter | |
2 | DS90CF384 |
National Semiconductor |
+3.3V Programmable LVDS Transmitter | |
3 | DS90CF384A |
National Semiconductor |
+3.3V LVDS Receiver | |
4 | DS90CF384A |
Texas Instruments |
+3.3V LVDS Receiver | |
5 | DS90CF384AQ |
Texas Instruments |
+3.3V LVDS Receiver | |
6 | DS90CF386 |
National Semiconductor |
+3.3V LVDS Receiver | |
7 | DS90CF386 |
Texas Instruments |
3.3-V LVDS Receiver | |
8 | DS90CF388 |
National Semiconductor |
Dual Pixel LVDS Display Interface | |
9 | DS90CF388 |
Texas Instruments |
Dual Pixel LVDS Display Interface | |
10 | DS90CF388A |
National Semiconductor |
Dual Pixel LVDS Display Interface/FPD-Link | |
11 | DS90CF363 |
National Semiconductor |
+3.3V LVDS Transmitter | |
12 | DS90CF363A |
National Semiconductor |
+3.3V Programmable LVDS Transmitter |