CY7C335 - Cypress Semiconductor

CY7C335 Universal Synchronous EPLD

The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very high performance state machines. The architecture of the CY7C335, consisting of the user-configurable output macrocell, bidirectional I/O capability, input registers, and three separat.

Features

• 100-MHz output registered operation
• Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock select multiplexer — Feed back multiplexer
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• — Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to implement JK or RS flip-flops and T or D registers Input multiplexer per pair of I/O macrocells allows I/O pin associated with a hidden macrocell state register to be saved for use as an input Four dedicated hidden registers Twelve ded.