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The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. Logic Block Diagram 1 (B6) INPUT/CLK 2 (A6) INPUT 32 (L4) INPUT 34 (L5) INPUT 128-.
• 128 macrocells in 8 LABs
• 8 dedicated inputs, 52 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 68-pin HLCC, PLCC, and PGA
Functional Description
The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions.
Logic Block Diagram
1 (B6) INPUT/CLK
2 (A6)
INPUT
32 (L4)
INPUT
34 (L5)
INPUT
128-Mac.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CY7C342 |
Cypress |
128-Macrocell MAX EPLDs |
|
| 2 | CY7C340 |
Cypress |
Multiple Array Matrix High-Density EPLDs |
|
| 3 | CY7C341B |
Cypress Semiconductor |
192-Macrocell MAX EPLD |
|
| 4 | CY7C343 |
Cypress |
64-Macrocell MAX EPLD |
|
| 5 | CY7C343B |
Cypress |
64-Macrocell MAX EPLD |
|
| 6 | CY7C344 |
Cypress Semiconductor |
32-Macrocell MAX EPLD |
|
| 7 | CY7C344B |
Cypress Semiconductor |
32-Macrocell MAX EPLD |
|
| 8 | CY7C345 |
Cypress |
128-Macrocell MAX EPLDs |
|
| 9 | CY7C346 |
Cypress Semiconductor |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) |
|
| 10 | CY7C325 |
Cypress |
Timing Control Unit |
|
| 11 | CY7C331 |
Cypress Semiconductor |
Asynchronous Registered EPLD |
|
| 12 | CY7C335 |
Cypress Semiconductor |
Universal Synchronous EPLD |
|